1. general description the 74vhc08-q100; 74vhct08-q100 are high-speed si-gate cmos devices and are pin compatible with low-power schottky ttl (lsttl). they are specified in compliance with jedec standard jesd7-a. the 74vhc08-q100; 74vhct08-q100 provide the quad 2-input and function. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? balanced propagation delays ? all inputs have a schmitt-trigger action ? inputs accept voltages higher than v cc ? input levels: ? the 74vhc08-q100 operates with cmos logic levels ? the 74vhct08-q100 operates with ttl logic levels ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 74vhc08-q100; 74vhct08-q100 quad 2-input and gate rev. 1 ? 20 december 2013 product data sheet
74vhc_vhct08_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 20 december 2013 2 of 15 nxp semiconductors 74vhc08-q100; 74vhct08-q100 quad 2-input and gate 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74vhc08d-q100 ? 40 ? cto+125 ? c so14 plastic small out line package; 14 leads; body width 3.9 mm sot108-1 74VHCT08D-Q100 74vhc08pw-q100 ? 40 ? cto+125 ? c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74vhct08pw-q100 74vhc08bq-q100 ? 40 ? cto+125 ? c dhvqfn14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 ? 3 ? 0.85 mm sot762-1 74vhct08bq-q100 fig 1. logic symbol fig 2. iec logic symbol fig 3. logic diagram (one gate) mna222 1a 1b 1y 2 1 3 2a 2b 2y 5 4 6 3a 3b 3y 10 9 8 4a 4b 4y 13 12 11 mna223 3 & & & & 2 1 6 5 4 8 10 9 11 13 12 mna221 a b y
74vhc_vhct08_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 20 december 2013 3 of 15 nxp semiconductors 74vhc08-q100; 74vhct08-q100 quad 2-input and gate 5. pinning information 5.1 pinning 5.2 pin description (1) the die substrate is attached to this pad using conductive die attach mate rial. it cannot be used as a supply pin or input. fig 4. pin configuration so14 and tssop14 fig 5. pin configuration dhvqfn14 9 + & |